Linear-Size Log-Depth Negation-Limited Inverter for k -Tonic Binary Sequences

A zero-one sequence x1, . . . , xn is k-tonic if the number of i’s such that xi 6= xi+1 is at most k. The notion generalizes well-known bitonic sequences. In negation-limited complexity, one considers circuits with a limited number of NOT gates, being motivated by the gap in our understanding of monotone versus general circuit complexity, and hoping to better understand the power of NOT gates. In this context, the study of inverters , i.e., circuits with inputs x1, . . . , xn and outputs ¬x1, . . . ,¬xn, is fundamental since an inverter with r NOTs can be used to convert a general circuit to one with only r NOTs. In particular, if linearsize log-depth inverter with r NOTs exists, we do not lose generality by only considering circuits with at most r NOTs when we seek superlinear size lower bounds or superlogarithmic depth lower bounds. Markov [JACM1958] showed that the minimum number of NOT gates necessary in an n-inverter is dlog2(n + 1)e. Beals, Nishino, and Tanaka [SICOMP98–STOC95] gave a construction of an ninverter with size O(n log n), depth O(log n), and dlog2(n + 1)e NOTs. We give a construction of circuits inverting k-tonic sequences with size O((log k) n) and depth O(log k log log n + log n) using log2 n + log2 log2 log2 n + O(1) NOTs. In particular, for the case where k = O(1), our k-tonic inverter achieves asymptotically optimal linear size and logarithmic depth. Our construction improves all the parameters of the k-tonic inverter by Sato, Amano, and Maruoka [COCOON06] with size O(kn), depth O(k log n), and O(k log n) NOTs. We also give a construction of k-tonic sorters achieving linear size and logarithmic depth with log2 log2 n+log2 log2 log2 n+O(1) NOT gates for the case where k = O(1). The following question by Turán remains open: Is the size of any depth-O(log n) inverter with O(log n) NOT gates superlinear?